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dual bootstrapped, 12 v mosfet driver with output disable adp3418 rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features all-in-one synchronous buck driver bootstrapped high-side drive 1 pwm signal generates both drives anticross-conduction protection circuitry output disable control turns off both mosfets to float the output per intel? vr 10 and amd opteron? specifications applications multiphase desktop cpu supplies single-supply synchronous buck converters general description the adp3418 is a dual, high voltage mosfet driver optimized for driving two n-channel mosfets, the two switches in a nonisolated, synchronous, buck power converter. each of the drivers is capable of driving a 3000 pf load with a 30 ns transition time. one of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated with floating high-side gate drivers. the adp3418 includes overlapping drive protection to prevent shoot-through current in the external mosfets. the od pin shuts off both the high- side and the low-side mosfets to prevent rapid output capacitor discharge during system shutdowns. the adp3418 is specified over the commercial temperature range of 0c to 85c and is available in an 8-lead soic package. functional block diagram 03229-b-001 r sq q cmp 1v vcc 6 delay delay 5 7 cmp 2 3 od 4 adp3418 c vcc bst vcc drvh sw drvl pgnd in 6 1 c bst1 r bst1 8 r g c bst2 d1 to inductor q1 q2 12v figure 1.
adp3418 rev. d | page 2 of 16 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 timing characteristics ..................................................................... 6 typical performance characteristics ............................................. 7 theory of operation ........................................................................ 9 low-side driver ............................................................................ 9 high-side driver ...........................................................................9 overlap protection circuit ...........................................................9 application information ................................................................ 10 supply capacitor selection ....................................................... 10 bootstrap circuit ........................................................................ 10 mosfet selection ..................................................................... 10 high-side (control) mosfets ................................................ 10 low-side (synchronous) mosfets ........................................ 11 pc board layout considerations ............................................. 12 outline dimensions ....................................................................... 14 ordering guide .......................................................................... 14 revision history 3/06rev. c to rev. d changes to features.......................................................................... 1 changes to table 1............................................................................ 3 changes to pc board layout considerations section .............. 12 changes to figure 15 caption....................................................... 13 3/05rev. b to rev. c updated format..................................................................universal added flex-mode u.s. patent 6683441 text ................................ 1 changes to table 2............................................................................ 4 7/04rev. a to rev. b updated figure 1; deleted figure 2 ............................................... 1 updated specifications .................................................................... 3 updated pin description................................................................. 5 updated theory of operation ........................................................ 9 updated applicatio ns section....................................................... 10 change to ordering guide............................................................ 14 4/04rev. 0 to rev. a updated format..................................................................universal change to general description ...................................................... 1 change to figure 13 ......................................................................... 8 change to ordering guide............................................................ 12 3/03revision 0: initial version
adp3418 rev. d | page 3 of 16 specifications 1 v cc = 12 v, bst = 4 v to 26 v, t a = 0c to 85c, unless otherwise noted. table 1. parameter symbol conditions min typ max unit supply supply voltage range v cc 4.15 13.2 v supply current i sys bst = 12 v, in = 0 v 3 6 ma od input input voltage high 2.6 v input voltage low 0.8 v input current ?1 +1 a propagation delay time t pdh od see figure 3 25 40 ns t pdl od see figure 3 20 40 ns pwm input input voltage high 3.0 v input voltage low 0.8 v input current ?1 +1 a high-side driver output resistance, sourcing current v bst ? v sw = 12 v 1.8 3.0 output resistance, sinking current v bst ? v sw = 12 v 1.0 2.5 transition times t rdrvh see figure 4 , v bst ? v sw = 12 v, c load = 3 nf 35 45 ns t fdrvh see figure 4 , v bst ? v sw = 12 v, c load = 3 nf 20 30 ns propagation delay 2 t pdhdrvh see figure 4 , v bst ? v sw = 12 v 10 40 65 ns t pdldrvh v bst ? v sw = 12 v 20 35 ns low-side driver output resistance, sourcing current 1.8 3.0 output resistance, sinking current 1.0 2.5 transition times t rdrvl see figure 4 , c load = 3 nf 25 35 ns t fdrvl see figure 4 , c load = 3 nf 21 30 ns propagation delay 2 t pdhdrvl see figure 4 5 30 60 ns t pdldrvl see figure 4 10 20 ns timeout delay sw = 5 v 240 ns sw = pgnd 90 120 ns 1 all limits at temperature extremes ar e guaranteed via correlation using standard statistical quality control (sqc). 2 for propagation delays, t pdh refers to the specified signal going high, and t pdl refers to it going low.
adp3418 rev. d | page 4 of 16 absolute maximum ratings table 2. parameter rating vcc ?0.3 v to +15 v bst dc ?0.3 v to v cc + 15 v <200 ns ?0.3 v to +36 v bst to sw ?0.3 v to +15 v sw dc ?5 v to +15 v <200 ns ?10 v to +25 v drvh (dc) sw ? 0.3 v to bst + 0.3 v drvh (<200 ns) sw ? 2 v to bst + 0.3 v drvl (dc) ?0.3 v to v cc + 0.3 v drvl (<200 ns) ?2 v to v cc + 0.3 v in, od ?0.3 v to +6.5 v operating ambient temperature range 0c to 85c operating junction temperature range 0c to 150c storage temperature range ?65c to +150c junction-to-air thermal resistance ( ja ) 2-layer board 123c/w 4-layer board 90c/w lead temperature (soldering, 10 sec) 300c infrared (15 sec) 260c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all voltages are referenced to pgnd. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pr ecautions are recommended to avoid performance degradation or loss of functionality.
adp3418 rev. d | page 5 of 16 pin configuration and fu nction descriptions 03229-b-002 drvh 8 sw 7 pgnd 6 drvl 5 bst 1 in 2 3 v cc 4 ad3418 top view (not to scale) od figure 2. pin configuration table 3. pin function descriptions pin o. neonic description 1 bst upper mosfet floating bootstrap supply. a capacitor connected between the bst and sw pins holds this bootstrapped voltage for the high-side mosfet as it is swi tched. the capacitor should be between 100 nf and 1 f. 2 in logic level input. this pin has primary control of the drive outputs. 3 od output disable. when low, this pin disables normal operation, forcing drvh and drvl low. 4 vcc input supply. this pin should be bypassed to pgnd with a ~1 f ceramic capacitor. 5 drvl synchronous rectifier drive. output drive for the lower (synchronous rectifier) mosfet. 6 pgnd power ground. should be closely connected to the source of the lower mosfet. 7 sw this pin is connected to the buck switching node, close to the upper mosfets source. it is the floating return for the upper mosfet drive signal. 8 drvh buck drive. output drive for the upper (buck) mosfet.
adp3418 rev. d | page 6 of 16 timing characteristics drvh o r drvl 90% 10% od t pdlod t pdhod 03229-b-003 figure 3. output di sable timing diagram in drvl drvh-sw sw t pdldrvl t fdrvl t pdhdrvh t rdrvh t pdldrvh t rdrvl t fdrvh t pdhdrvl v th 1v v th 03229-b-004 figure 4. timing diagramtiming is referenced to the 90% and 10% points, unless otherwise noted
adp3418 rev. d | page 7 of 16 typical performance characteristics 2 3 1 drvl drvh in 03229-b-005 figure 5. drvh rise and drvl fall times 03229-b-006 2 3 1 drvl drvh in figure 6. drvh fall and drvl rise times 03229-b-007 junction temperature (c) 125 0 25 50 75 100 rise time (ns) 40 35 30 25 20 v cc = 12v c load = 3nf drvh drvl figure 7. drvh and drvl rise times vs. junction temperature 03229-b-008 junction temperature (c) 125 0 25 50 75 100 fall time (ns) 26 24 22 20 18 16 drvl drvh v cc = 12v c load = 3nf figure 8. drvh and drvl fall times vs. junction temperature 03229-b-009 load capacitance (nf) 5 1234 rise time (ns) 60 50 40 30 20 10 t a =25c v cc = 12v drvh drvl figure 9. drvh and drvl rise times vs. load capacitance 03229-b-010 load capacitance (nf) 5 1234 fall time (ns) 35 30 25 20 15 10 t a =25c v cc = 12v drvl drvh figure 10. drvh and drvl fall times vs. load capacitance
adp3418 rev. d | page 8 of 16 03229-b-011 frequency (khz) 1200 0 200 400 600 800 1000 supply current (ma) 60 40 20 0 t a =25c v cc = 12v c load = 3nf figure 11. supply current vs. frequency 03229-b-012 junction temperature (c) 125 0 25 50 75 100 supply current (ma) 16 15 14 13 12 v cc = 12v c load = 3nf f in = 250khz figure 12. supply current vs. junction temperature 03229-b-013 v cc voltage (v) 5 01234 drvl output voltage (v) 5 4 3 2 1 0 t a = 25c c load = 3nf figure 13. drvl output voltage vs. supply voltage
adp3418 rev. d | page 9 of 16 theory of operation the adp3418 is a dual mosfet driver optimized for driving two n-channel mosfets in a synchronous buck converter topology. a single pwm input signal is all that is required to properly drive the high-side and the low-side mosfets. each driver is capable of driving a 3 nf load at speeds up to 500 khz. a more detailed description of the adp3418 and its features follows. refer to figure 1 . low-side driver the low-side driver is designed to drive a ground-referenced n-channel mosfet. the bias to the low-side driver is internally connected to the v cc supply and pgnd. when the driver is enabled, the drivers output is 180 out of phase with the pwm input. when the adp3418 is disabled, the low-side gate is held low. high-side driver the high-side driver is designed to drive a floating n-channel mosfet. the bias voltage for the high-side driver is developed by an external bootstrap supply circuit, which is connected between the bst and sw pins. the bootstrap circuit comprises a diode, d1, and bootstrap capacitor, c bst1 . c bst2 and r bst are included to reduce the high- side gate drive voltage and limit the switch node slew rate (referred to as a boot-snap? circuit, see the application information section for more details). when the adp3418 starts up, the sw pin is at ground; therefore, the bootstrap capacitor charges up to v cc through d1. when the pwm input goes high, the high-side driver begins to turn on the high-side mosfet, q1, by pulling charge out of c bst1 and c bst2 . as q1 turns on, the sw pin rises up to v in , forcing the bst pin to v in + v c (bst) , which is enough gate-to-source voltage to hold q1 on. to complete the cycle, q1 is switched off by pulling the gate down to the voltage at the sw pin. when the low-side mosfet, q2, turns on, the sw pin pulls to ground. this allows the bootstrap capacitor to charge up to v cc again. the high-side drivers output is in phase with the pwm input. when the driver is disabled, the high-side gate is held low. overlap protection circuit the overlap protection circuit prevents both of the main power switches, q1 and q2, from being on at the same time. this is done to prevent shoot-through currents from flowing through both power switches and the associated losses that can occur during their on/off transitions. the overlap protection circuit accomplishes this by adaptively controlling the delay from the q1 turn off to the q2 turn on, and by internally setting the delay from the q2 turn off to the q1 turn on. to prevent the overlap of the gate drives during the q1 turn off and the q2 turn on, the overlap circuit monitors the voltage at the sw pin. when the pwm input signal goes low, q1 begins to turn off (after propagation delay). before q2 can turn on, the overlap protection circuit ensures that sw has first gone high and then waits for the voltage at the sw pin to fall from v in to 1 v. once the voltage on the sw pin falls to 1 v, q2 begins to turn on. if the sw pin had not gone high first, the q2 turn on is delayed by a fixed 120 ns. by waiting for the voltage on the sw pin to reach 1 v or for the fixed delay time, the overlap protection circuit ensures that q1 is off before q2 turns on, regardless of variations in temperature, supply voltage, input pulse width, gate charge, and drive current. if sw does not go below 1 v after 240 ns, drvl turns on. this can occur if the current flowing in the output inductor is negative and is flowing through the high-side mosfet body diode. to prevent the overlap of the gate drives during the q2 turn off and the q1 turn on, the overlap circuit provides an internal delay that is set to 40 ns. when the pwm input signal goes high, q2 begins to turn off (after a propagation delay), but before q1 can turn on, the overlap protection circuit waits for the voltage at drvl to drop to approximately one sixth of v cc . once the voltage at drvl has reached this point, the overlap protection circuit waits for the 40 ns internal delay time. once the delay period has expired, q1 turns on.
adp3418 rev. d | page 10 of 16 application information supply capacitor selection for the supply input (v cc ) of the adp3418, a local bypass capacitor is recommended to reduce the noise and to supply some of the peak currents drawn, such as a 4.7 f, low esr capacitor. multilayer ceramic chip (mlcc) capacitors provide the best combination of low esr and small size. keep the ceramic capacitor as close as possible to the adp3418. bootstrap circuit the bootstrap circuit uses a charge storage capacitor (c bst ) and a diode, as shown in figure 1 . these components can be selected after the high-side mosfet is chosen. the bootstrap capacitor must have a voltage rating that is able to handle twice the maximum supply voltage. a minimum 50 v rating is recommended. the capacitor values are determined by: gate gate bst2 bst1 v q cc =+ 10 (1) d cc gate bst2 bst1 bst1 vv v cc c ? = + (2) where: q gate is the total gate charge of the high-side mosfet at v gate . v gate is the desired gate drive voltage (usually in the 5 v to 10 v range, 7 v being typical). v d is the voltage drop across d1. rearranging equation 1 and equation 2 to solve for c bst1 yields d cc gate bst vv q c ? = 10 1 c bst2 can then be found by rearranging equation 1 as bst1 gate gate bst2 c v q c ?= 10 for example, an ntd60n02 has a total gate charge of approximately 12 nc at v gate = 7 v. using v cc = 12 v and v d = 1 v, one finds c bst1 = 12 nf and c bst2 = 6.8 nf. good quality ceramic capacitors should be used. r bst is used for slew rate limiting to minimize the ringing at the switch node. it also provides peak current limiting through d1. an r bst value of 1.5 to 2.2 is a good choice. the resistor needs to be able to handle at least 250 mw due to the peak currents that flow through it. a small signal diode can be used for the bootstrap diode due to the ample gate drive voltage supplied by v cc . the bootstrap diode must have a minimum 15 v rating to withstand the maximum supply voltage. the average forward current is estimated by max gate avgf fqi = )( (3) where f max is the maximum switching frequency of the con- troller. the peak surge current rating is calculated by bst d cc peakf r v v i ? = )( (4) mosfet selection when interfacing the adp3418 to external mosfets, there are a few considerations that the designer should be aware of. these help make a more robust design that minimizes stresses on both the driver and mosfets. these stresses include exceeding the short-time duration voltage ratings on the driver pins as well as the external mosfet. it is also highly recommended to use the boot-snap circuit to improve the interaction of the driver with the characteristics of the mosfets. if a simple bootstrap arrangement is used, make sure to include a proper snubber network on the sw node. high-side (control) mosfets the high-side mosfet is usually high speed to minimize switching losses (see any adi flex-mode? 1 controller data sheet for more details on mosfet losses). this usually implies a low gate resistance and a low input capacitance/charge device. yet, there is also a significant source lead inductance that can exist. this depends mainly on the mosfet package; it is best to contact the mosfet vendor for this information. the adp3418 drvh output impedance and the input resistance of the mosfets determine the rate of charge delivery to the gates internal capacitance, which determines the speed at which the mosfets turn on and off. however, due to potentially large currents flowing in the mosfets at the on and off times (this current is usually larger at turn off due to ramping up of the output current in the output inductor), the source lead inductance generates a significant voltage across it when the high-side mosfets switch off. this creates a significant drain-source voltage spike across the internal die of the mosfets and can lead to a catastrophic avalanche. the mechanisms involved in this avalanche condition can be referenced in literature from the mosfet suppliers. 1 flex-mode is protecte d by u.s. patent 6,683,441.
adp3418 rev. d | page 11 of 16 the mosfet vendor should provide a maximum voltage slew rate at the drain current rating such that this can be designed around. once this specification is had, the next step is to determine the maximum current expected to be seen in the mosfet. this can be done by () out max max out cc dc max lf d vvphaseperii ?+ = )( (5) where: d max is determined for the vr controller being used with the driver. note that this current is divided roughly equally between mosfets if more than one is used (assume a worst-case mismatch of 30% for design margin). l out is the output inductor value. when producing the design, there is no exact method for calculating the dv/dt due to the parasitic effects in the external mosfets as well as the pcb. however, it can be measured to determine if it is safe. if it appears the dv/dt is too fast, an optional gate resistor can be added between drvh and the high-side mosfets. this resistor slows down the dv/dt, but it also increases the switching losses in the high-side mosfets. the adp3418 has been optimally designed with internal drive impedance that works with most mosfets to switch them efficiently while minimizing dv/dt. however, some high speed mosfets can require this external gate resistor, depending on the currents being switched in the mosfet. low-side (synchronous) mosfets the low-side mosfets are usually selected to have a low on resistance to minimize conduction losses. this usually implies a large input gate capacitance and gate charge. the first concern is to make sure the power delivery from the adp3418s drvl does not exceed the thermal rating of the driver (see any adi flex-mode controller data sheet for details). the next concern for the low-side mosfets is based on preventing them from inadvertently being switched on when the high-side mosfet turns on. this occurs due to the drain- gate (miller, also specified as c rss ) capacitance of the mosfet. when the drain of the low-side mosfet is switched to v cc by the high-side turning on (at a rate dv/dt), the internal gate of the low-side mosfet is pulled up by an amount roughly equal to v cc (c rss /c iss ). it is important to make sure this does not put the mosfet into conduction. another consideration is the nonoverlap circuitry of the adp3418, which attempts to minimize the nonoverlap period. during the state of the high-side turning off to low-side turning on, the sw pin is monitored (as well as the conditions of sw prior to switching) to adequately prevent overlap. however, during the low-side turn off to high-side turn on, the sw pin does not contain information for determining the proper switching time; therefore, the state of the drvl pin is monitored to go below one sixth of v cc and then a delay is added. however, due to the miller capacitance and internal delays of the low-side mosfet gate, one must ensure that the miller to input capacitance ratio is low enough, and that the low-side mosfet internal delays are not large enough, to allow accidental turn on of the low-side when the high-side turns on. a spreadsheet is available from adi to assist designers with the proper selection of low-side mosfets.
adp3418 rev. d | page 12 of 16 pc board layout considerations use the following general guidelines when designing printed circuit boards: ? trace out the high current paths and use short, wide (>20 mil) traces to make these connections. ? connect the pgnd pin of the adp3418 as close as possible to the source of the lower mosfet. ? the v cc bypass capacitor should be located as close as possible to the vcc and pgnd pins. ? use vias to other layers when possible to maximize thermal conduction away from the ic. the circuit in figure 15 shows how four drivers can be combined with the adp3188 to form a total power conversion solution for generating v cc (core) for an intel cpu that is vr 10.x-compliant. figure 14 shows an example of the typical land patterns based on the guidelines given previously. for more detailed layout guidelines for a complete cpu voltage regulator subsystem, refer to the adp3188 data sheet. d1 c bst2 c bst1 r bst c vcc 03229-b-014 figure 14. external component placement example for the adp3418 driver
adp3418 rev. d | page 13 of 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 d5 1n4148 c19 4.7 f q13 ntd60n02 q15 ntd110n02 q16 ntd110n02 c16 6.8nf c17 4.7 f u5 adp3418 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l5 320nh/1.4m rth1 100k , 5% ntc r6 2.2 c20 12nf d4 1n4148 c15 4.7 f q9 ntd60n02 q11 ntd110n02 q12 ntd110n02 c14 6.8nf c13 4.7 f u4 adp3418 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l4 320nh/1.4m r5 2.2 c16 12nf d3 1n4148 c11 4.7 f q5 ntd60n02 q7 ntd110n02 q8 ntd110n02 c10 6.8nf c9 4.7 f u3 adp3418 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 d1 1n4148 l3 320nh/1.4m r4 2.2 c12 12nf d2 1n4148 c7 4.7 f q1 ntd60n02 q3 ntd110n02 q4 ntd110n02 c6 6.8nf c5 4.7 f u2 adp3418 bst 1 in 2 3 vcc 4 drvh sw pgnd drvl 8 7 6 5 l4 320nh/1.4m r3 2.2 c8 12nf + + c24 c31 10 f 18 mlcc in socket v cc (core) 0.8375 v ? 1.6v 95a tdc, 119a pk v cc (core) rtn 560 f/4v 8 sanyo sepc series 5m each u1 adp3188 vid4 vid3 vid2 vid1 vid0 vid5 fbrtn fb comp pwrgd en delay rt rampadj vcc pwm1 pwm2 pwm3 pwm4 sw1 sw2 sw3 sw4 gnd cscomp cssum csref ilimit r ph1 158k , 1% r ph2 158k , 1% r ph3 158k , 1% r ph4 158k , 1% r cs2 84.5k c a 470pf c b 470pf r cs1 35.7k r a 12.1k r b 1.21k c cs2 1.5nf c fb 22pf c cs1 560pf c22 1nf r lim 150k 1% c23 1nf c21 1nf power good enable from cpu c ldy 39nf r ldy 470k r t 137k 1% r2 137k 1% + c3 100 f c4 1 f ++ c1 c2 li 370nh 18a 2700mf/16v/3.3a 2 sanyo mv-wx series v in 12v v in rtn 0 3229-b-015 od od od od figure 15. vr 10.x-compliant intel cpu supply circuit
adp3418 rev. d | page 14 of 16 outline dimensions 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2440) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-012-aa figure 16. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model temperature range package description package option ADP3418KRZ 1 0c to 85c 8-lead soic_n r-8 ADP3418KRZ-reel 1 0c to 85c 8-lead soic_n r-8 1 z = pb-free part.
adp3418 rev. d | page 15 of 16 notes
adp3418 rev. d | page 16 of 16 t notes ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c03229C0C3/06(d) ttt

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